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(R)
ISL6111
Data Sheet March 2004 FN9146.1
Current Regulated PCI Hot Plug Power Switch Controller
The ISL6111 is designed for use in PCI and PCI-X applications where active current regulation protection of the motherboard from an abnormal PCI load card is desired. With the addition of two discrete power MOSFETs and a few passive components, the ISL6111 provides power control for the four legacy supplies (-12V, +12V, +5V, +3.3V) to a PCI or PCI-X slot. This IC integrates the +12V and -12V current sensing and regulation switches. On the 25W capable 3.3V and 5V rails, current regulation (CR) protection is provided by sensing the voltage across external current-sense resistors and modulation of the gate voltage bias on the external N-channel power MOSFETs. During initial power-up of the +12V bias supply, the ENABLE (EN), Power Good (PG), fault monitoring and reporting function functions are inhibited if bias voltage <10V. Once the FETs are enabled they are soft started into the load thus eliminating supply rail disturbances. Upon a failure that quickly causes a load current greater than the programmed CR level on any voltage supply, the ISL6111 enters its current regulation (CR) mode, limiting the load current to the user programmed level for the user determined period of time. The CR level and duration are set by a single resistor and capacitor respectively. At the end of the CR duration all the switches will latch off pulling the outputs low along with the CRTIM (current regulation timer) and FLTN (fault not) pins indicating a latch-off due to an over current (OC) condition. If a severe OC condition should occur, then the ISL6111 immediately latches off all outputs and sets the FLTN output low. During operation, if any of the positive voltages falls below the minimum PCI specified levels the power good (PG) output will pull low indicating a non compliant voltage to a load. PG is an open drain output as is FLTN. The CRSET pin allows programming of the current regulation levels to be scaled up or down from the PCI specified levels via a resistor connected between the CRSET pin and ground. All faults and latches are cleared by ENABLE being deasserted low.
Features
* Active Current Regulation for Protection * Adjustable Current Regulation Duration and Magnitude * Internal MOSFET Switches for +12V and -12V Outputs * Provides Fault Isolation * Adjustable Turn-On Slew Rate * Minimum Parts Count Solution * No Charge Pump * 1s Response Time to Over Current * Pb-Free leadframe
Applications
* PCI * PCI-X 1.0
Ordering Information
PART NUMBER ISL6111CRZA (see Note) ISL6111EVAL2 TEMP. RANGE (C) 0 to 75 PACKAGE 20 Ld 5x5 QFN (Pb-Free) PKG. DWG. # L20.5x5
Evaluation Platform
NOTE: Intersil Lead-Free products employ special lead-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and lead-free soldering operations. Intersil Lead-Free products are MSL classified at lead-free peak reflow temperatures that meet or exceed the lead-free requirements of IPC/JEDEC J Std-020B.
Pinout
ISL6111 (5x5 QFN) TOP VIEW
3VISEN M12VO 17 CRSET M12VI 16 15 M12VG 14 GND_A -12V 13 12VO_B 12 12VO_A 11 5VG 6 CRTIM 7 FLTN 8 5VISEN 9 5VS 10 EN
20 3VG 12VI_A GND_B 12VI_B PGOOD 1 2 3 4 5
3VS
19
18
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6111 Typical Application
(Note 1) (Note 1) 3.3V SUPPLY 3.3V, 7.6A OUT (Note 1) 12V, 0.5A OUT (Note 1) -12V, 0.1A OUT (Note 1) 5V, 5A OUT (Note 1) RSENSE_5 5V SUPPLY
RSENSE_3
ENABLE INPUT -12V SUPPLY
EN CRTIM 3VG
ISL6111 M12VO M12VG 5VG GND(2) 12VO(2) 5VISEN 5VS CRSET RCRSET (Note 1) 5nF
M12VIN
3VISEN 12V SUPPLY V(I/O) V(I/O) 12VI(2) 3VS PG FLTN CCRTIM (Note 2)
FAULTN POWER GOOD
NOTES: 1. See Table 1 for CR level formula 2. See Table 2 for CR duration vs CTIM. FIGURE 1. ISL6111 TYPICAL APPLICATION SCHEMATIC
2
ISL6111 Simplified Schematic
5VREF RESET FAULT LATCH PGOOD FAULTN
COMP
+ 4.6V
COMP
+ 2.9V
+ -
20A CRTIM 12VIN 12VIN 12VIN 5VREF 5V ZENER REFERENCE
+ + -
+
-
+ -
+ 12VIN 12VIN POWER-ON RESET LOW WHEN 12VIN < 10V + COMP 12VIN + AMP 3VG + 3VS
+
-
12VIN
+ -
+ 100A VOCSET CRSET HIGH = FAULT 12VO HIGH = SWITCHES ON ENABLE WOC COMP + + GND + COMP + 0.7 AMP M12VG M12VIN M12VO + M12VIN + COMP + 12VIN AMP 12VIN 0.3
12VIN
3
+
-
+ -
12VIN
COMP +
2.8V WOC COMP
COMP
+ 10.6V
+ COMP
5VS 12VIN + AMP 5VG
WOC COMP
5VISEN
3VISEN WOC COMP
ISL6111 Pin Descriptions
PIN NO. 1 DESIGNATOR 3VG FUNCTION FUNCTION DESCRIPTION 3.3V FET Gate Output Drives the gate of the 3.3V MOSFET. Connect to the gate of the external N-Channel MOSFET. At turn-on the FET gate capacitance will be charged to 12VIN voltage by a 10A current source. An optional capacitor from this node to ground will adjust the turn-on ramp. 12V Input IC Ground Reference Power Good Current Regulation Duration Input Fault Indication 5V Current Sense 5V Source Enable Input 5V FET Gate Output +12V IC bias supply and power supply rail input to internal power switch. Connect to common of power supplies. An open drain logic output that is released to indicate all positive voltage outputs are above minimum PCI spec. Connect to V(I/O) through resistor. An external capacitor from this pin to ground sets the current regulation duration before latch off. This output will pull low after the current regulation duration has expired. CR duration = 150K x CTIM. This pin sources 20A and has a threshold trip voltage of 2.83V. A fault-not open drain output. Latches low once current regulation time has expired. Reset by 12VIN POR condition or enable input signaled low. Connect to V(I/O) through resistor. Connect to the load side of the current sense resistor in series with source of external 5V MOSFET. Monitors voltage to load. Connect to source of 5V MOSFET switch. This connection along with 5VISEN senses the voltage drop across the sense resistor. Controls all four internal and external switches, initiates turn-on/off Drives the gate of the 5V MOSFET. Connect to the gate of the external N-Channel MOSFET. At turn-on the FET gate capacitance will be charged to 12VIN voltage by a 10A current source. An optional capacitor from this node to ground will adjust the turn-on ramp Switched 12V output.
2, 4 3, 14 5 6
12VI GND PGOOD CRTIM
7 8 9 10 11
FLTN 5VISEN 5VS EN 5VG
12, 13 15 16 17 18 19 20
12VO M12VG M12VI M12VO CRSET 3VISEN 3VS
Switched 12V Output
Gate of Internal NMOS Connect a 5nF capacitor between M12VG and ground to stabilize the start-up ramp for the M12V supply. This capacitor is charged with 25A during start-up. -12V Input Switched -12V Output -12V Supply Input. Also provides power to the -12V current regulation circuitry. Switched -12V Output.
Current Regulation Set Program current regulation levels for all four switches by connecting a resistor to GND. This pin sources 100A. See Table 1 for CR level setting formulae. 3.3V Current Sense 3.3V Source Connect to the load side of the current sense resistor in series with source of external 3.3V MOSFET. Monitors voltage to load. Connect to source of 3.3V MOSFET. This connection along with 3VISEN senses the voltage drop across the sense resistor.
4
ISL6111
Absolute Maximum Ratings
12VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +15.0V 12VO, 3VG, 5VG . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 12VI+0.5V M12VI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -14.0V to +0.5V M12VO, M12VG. . . . . . . . . . . . . . . . . . . . . . . VM12VI-0.5V to +0.5V 3VISEN, 5VISEN . . . . . . . . . . . -0.5V to the Lesser of 12VI or +7.0V Voltage, Any Other Pin. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V 12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3A M12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8A ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4KeV (HBM)
Thermal Information
Thermal Resistance (Typical, Notes 3, 5) JA (C/W) JC (C/W) QFN Package. . . . . . . . . . . . . . . . . . . . 31 2.5 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C
Operating Conditions
12VIN Supply Voltage Range . . . . . . . . . . . . . . . . +10.8V to +13.2V 5V and 3.3V Input Supply Tolerances. . . . . . . . . . . . . . . . . . . . . . 10% 12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +0.5A M12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +0.1A Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . . 0C to 85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 4. All voltages are relative to GND, unless otherwise specified. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER 5V/3.3V CURRENT CONTROL 5V Current Regulation Threshold Voltage 5V WOC Threshold Voltage 5V Current Regulation Level
Nominal 5.0V and 3.3V Input Supply Voltages, 12VI = 12V, M12VI = -12V, TA = TJ = 0 to 75C, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
VOC5V VOC5V_woc ICR5V_3 ICR5V_35 ICR5V_4 ICR5V_46
VCRSET = 0.3V VCRSET = 0.3V RCRSET = 3K (See Figure 1, Typical Application) RCRSET = 3.5K (See Figure 1, Typical Application) RCRSET = 4K (See Figure 1, Typical Application) RCRSET = 4.64K (See Figure 1, Typical Application) di/dt = 0.001A/s, Current Trip Level/Current Regulation Level dCT/85C (See Figure 1, Typical Application)
-
26.5 49
4.64 -
mV mV A A A A % mA/C V ms ms mV mV A A A A %
4.51
5.3 5.8 6.4 7.2 90 3.5 4.57 7 6 39.5 80 7.9 8.7 9.8 10.9 90
Slow Ramping Current Trip Level Current Trip Level Temp Coeff. 5V Undervoltage Threshold 5V Turn-On Time (EN to 5VOUT = 4.5V) 5V Turn-Off Time (EN to 5VOUT = 0.5V) 3.3V Current Regulation Threshold Voltage 3.3V WOC Threshold Voltage 3.3V Current Regulation Level
CT/CR CT_t V5VUV tON5V tOFF5V VOC3V VOC3V_woc ICR3V_3 ICR3V_35 ICR3V_4 ICR3V_46
C5VOUT = 3300F, RL = 1,VCRSET = 0.35V C5VOUT = 3300F, RL = 1,VCRSET = 0.35V VCRSET = 0.3V VCRSET = 0.3V RCRSET = 3K (See Figure 1, Typical Application) RCRSET = 3.5K (See Figure 1, Typical Application) RCRSET = 4K (See Figure 1, Typical Application) RCRSET = 4.64K (See Figure 1, Typical Application) di/dt = 0.001A/s, Current Trip Level/Current Regulation Level
-
Slow Ramping Current Trip Level
CT/CR
5
ISL6111
Electrical Specifications
PARAMETER Current Trip Level Temp Coeff. 3.3V Undervoltage Threshold 3.3V Turn-On Time (EN to 3VOUT = 3V) 3.3V Turn-Off Time (EN to 3VOUT = 3V) Current Limit Amp Offset Voltage Current Limit Amp Offset Voltage EXTERNAL GATE DRIVE Response Time to OC Response Time to OC Turn-off Time To WOC Turn-On Current Turn-On Time (EN to VG = 1V) Pull Down Current WOC Pull Down Current High Voltage Low Voltage +12V SUPPLY CONTROL On Resistance of Internal PMOS @ 0.5A Current Regulation Level rDS(ON)12 TA = TJ = 25C TA = TJ = 85C ICR12V ICR12V_35 ICR12V_4 ICR12V_45 Slow Ramping Current Trip Level Current Trip Level Temp Coeff. 12V Undervoltage Threshold Vout Turn-On Time Vout Turn-On Time Vout Turn-Off Time Vout Turn-Off Time WOC Vout Turn-Off Voltage -12V SUPPLY CONTROL On Resistance of Internal NMOS @ 0.1A Current Regulation Level rDS(ON)M12 TA = TJ = 25C TA = TJ = 85C ICMR12V ICMR12V_35 ICMR12V_4 ICMR12V_45 VCRSET = 0.3V RCRSET = 3.5K RCRSET = 4.0K RCRSET = 4.64K 0.085 0.7 0.9 0.11 0.115 0.120 0.140 0.135 A A A A CT/CR 12VCT_t V12VUV tON12V tON12V tOFF12V tOFF12VWOC VOFF12 12V Rising 10% - 90%, C12VO = 50F, RL = 25 12V Rising 10% - 90%, C12VO = 300F, RL = 25 12V Falling 90% - 10%, C12VO = 300F, RL = 25 12V Falling 90% - 10%, C12VO = 300F, RL = 25 Vout when off VCRSET = 0.3V RCRSET = 3.5K RCRSET = 4.0K RCRSET = 4.64K di/dt = 0.001A/s, Current Trip Level/Current Regulation Level dCT/85C 0.45 10.57 0.3 0.35 0.52 0.54 0.56 0.62 80 0.6 10.7 1.7 5 15 35 0.3 0.55 10.9 A A A A % mA/C V ms ms ms s V pd_oc_amp pd_oc_gate_10 pd_woc_amp IGATE tONGATE VGATE to 11V VGATE to 10V VGATE to 2V VGATE to = 6V 3VG, 5VG Rising to 1V 8 20 0.5 VDD-1V 100 10 1 10 400 35 0.8 VDD 0.5 12 50 1.5 0.7 ns s s A s mA A V V Nominal 5.0V and 3.3V Input Supply Voltages, 12VI = 12V, M12VI = -12V, TA = TJ = 0 to 75C, Unless Otherwise Specified (Continued) SYMBOL CT_t V3VUV tON3V tOFF3V Vio_ft Vio_pt C3VOUT = 3300F, RL = 0.5, VCRSET = 0.35V C3VOUT = 3300F, RL = 0.5, VCRSET = 0.35V VS - VISEN VS - VISEN, TJ = 15C to 55C TEST CONDITIONS dCT/85C (See Figure 1, Typical Application) MIN 2.7 -6 -2 TYP 3.5 2.8 6 5 0 0 MAX 2.9 6 2 UNITS mA/C V ms ms mV mV
OC_GATE_I_4V Overcurrent WOC_GATE_I_4V Severe Overcurrent VG_high VG_low Gate On Voltage Gate Off Voltage
6
ISL6111
Electrical Specifications
PARAMETER Slow Ramping Current Trip Level Current Trip Level Temp Coeff. Gate Turn-Off Time Gate Response Time To Overcurrent Gate Response Time to WOC Gate Output Charge Current Vout Turn-On Time Vout Turn-On Time Vout Turn-Off Time Vout Turn-Off Time WOC Vout Turn-Off Voltage M12VIN Input Bias Current CONTROL AND I/O PINS CRSET Current Source Rising ENABLE Threshold Voltage Falling ENABLE Threshold Voltage ENABLE Threshold Voltage Hysteresis Enable to Output Turn-on Prop. Delay Power Good Output Low Voltage Power Good Output Pull-down Current Power Good to Vout Falling Response Time Power Good to Vout Rising Response Time FAULTN Output Low Voltage FAULTN Output Pull-down Current FAULTN Output Response Time CRTIM Charging Current Current Regulation Time-Out Threshold BIAS 12V Lock Out Threshold 12V Power On Reset Threshold 12V Reset Threshold Hysteresis 12V Disabled Supply Current VPOR,THrise VPOR,THfall VPOR,HYS IDIS 12VIN, EN = 0V VCC Voltage Rising VCC Voltage Falling 9.88 9.17 10.1 9.3 0.69 3.3 10.5 9.43 6 V V V mA ICRSET VTH_EN_L2H VTH_EN_H2L VTH_EN_HYS Tpd_EN VPG,L IPG tUV2PG_fall tUV2PG_rise VFLTN,L IFLTN tOC2FLTN CRTIM_ichg0 CRTIM_Vth CTIM_Vth to FLTN low VCTIM = 0V CTIM Voltage Vout < UV Vth to PG low Vout >UV Vth to PG high IFLTN = 5mA Enable high to start of output turn=on IPG = 5mA 90 1.5 1.2 2.74 100 1.7 1.5 0.2 2 0.6 40 500 8 0.6 40 26 2.83 110 2.0 1.9 0.3 0.75 0.75 1 2.92 A V V V ms V mA ns ms V mA s A V Nominal 5.0V and 3.3V Input Supply Voltages, 12VI = 12V, M12VI = -12V, TA = TJ = 0 to 75C, Unless Otherwise Specified (Continued) SYMBOL CT/CR M12VCT_t tOFFM12VG tOC2M12VG tWOC2M12VG ICM12VG tONM12VO tONM12VO tOFFM12VO ENABLE = High, VM12VG = -10V -12V Falling 90% - 10%, CM12VO = 50F, RL = 120 -12V Falling 90% - 10%, CM12VO = 150F, RL =120 -12V Rising 10% - 90%, CM12VO = 150F, RL = 120 TEST CONDITIONS di/dt = 0.001A/s, Current Trip Level/Current Regulation Level dCT/85C CM12VG = 0.005F, M12VG Falling 90% to 10% MIN 4.5 TYP 90 0.1 330 1 400 102 11 35 40 15 -0.6 5.3 MAX 1 7 UNITS % mA/C ns s ns A ms ms ms s V mA
tOFFM12VOWOC -12V Rising 10% - 90%, CM12VO = 150F, RL = 120 VOFFM12VO IBM12VIN Vout when off ENABLE = High
7
ISL6111 Introduction
The ISL6111, is an IC device designed to provide control and protection of the four legacy PCI power supplies (+12V, -12V, +5V and +3.3V) for a single PCI or PCI-X slot. Unlike the widely used HIP1011, this device employs an active current regulation (CR) method to provide system protection against load faults. Figure 1 illustrates the typical implementation of the ISL6111. duration is user defined by the capacitor value on the CRTIM pin. Once in CR mode, the CRTIM pin charges the capacitor with a 20A current until the voltage on CRTIM rises to ~2.8V, at which time a turn-off latch is set on all 4 power FET switches. Also at this time the open drain fault (FLTN) output is pulled low signalling a latched off state. After a fault has been asserted and FLTN is latched low, cycling ENABLE low will clear the FLTN latch. On-chip references in the ISL6111 are used to monitor the +5V, +3.3V and +12V outputs for under voltage (UV) conditions. Once an UV condition is present the open drain power good (PGOOD) output will pull low to indicate this.
Key Feature Description and Operation
The ISL6111, 2 power MOSFETs and a few passive components as configured in Figure 1, completes a power control solution for the legacy supplies to a PCI slot. It provides protection via a programmable maximum current regulation (CR) level to the load for each supply. For the 3.3V and 5V supplies, current monitoring is provided by sensing the voltage across external current-sense resistors, and CR protection is provided by active voltage modulation of external N-Channel MOSFETs. For the +12V and -12V supplies, current monitoring and CR protection are provided internally. During initial power-up of the main bias supply pins (12VI), the ENABLE input function is inhibited from turning on the switches, this latch is held in the reset state until the bias voltage is greater than 10V (POR rising). Additionally the power good and fault reporting functions are also disabled at this time and during the soft start duration. During turn-on of the supplies onto their capacitive loads the current limiting fail-safe is engaged, this limited current gives a voltage ramp-up slew rate centered within the PCI specs. As the startup is current-limited, the CRTIM timer is engaged during the entire startup, as it should be. This eliminates the otherwise destructive case of starting up into a dead short. Depending on loading, the positive 3 supplies will start up and exit current limiting in about 6ms -10ms. The -12V supply will take much longer, as it has a fraction of the available charging current into a potentially relatively very large load capacitance, and the voltage has to slew to -12V. The -12V turn-on duration can thus be several times as long extending to ~50ms for a very capacitive (147F) load in conjunction with a maximum current load. In addition if the CR level is too low then it's possible that the load capacitance cannot fully charge in the allowed for time, this is the consequence of the current regulation limiting protection. Once turned on, any subsequent over current (OC) condition on any output results in the affected switch (external or internal) to be put into its linear mode of operation, and the current is regulated to the level determined by the choice of external CRSET resistor value. An OC condition is defined as a current level > the programmed CR level and that transitions through the CR level with a quick ramp, <0.5s. This CR level is maintained until the OC condition passes or the CR duration expires, whichever comes first. The CR 8
Customizing Circuit Performance
Setting Current Regulation (CR) Level
The ISL6111 allows for easy and simultaneous custom programming of the CR levels of all 4 supplies by simply changing the resistor value between CRSET, (pin 18), and ground. The RCRSET value and the CRSET 100A current source create a reference voltage that is used in each of four comparators. The IR voltages developed across the 3.3V and 5V sense resistors are applied to the inputs of their respective comparators opposite this reference voltage. The +12V and -12V currents are sensed internally with pilot devices. Because of the internal current monitoring of the +12V and -12V switches, their programming flexibility is limited to RCRSET changes whereas the 3.3V and 5V over current regulation levels depend on both RCRSET, and the value chosen for each sense resistor. See Table 1 to determine CR protection levels relative to choice of RCRSET and RSENSE values. Over current design guidelines and recommendations are as follows: 1. For PCI applications, set RCRSET to 4.22k, and use 5m 1% sense resistors (see Figure 20). This RCRSET value provides a nominal current trip level 110% to 130% higher than the maximum specified current, to ensure full current range use by the PCI load. The ISL6111 will trip off on a slow increasing current ramp approximately 10% to 20% lower than set CR level. 2. For non PCI specified applications, the following precautions and limitations apply: A. Do not exceed the maximum power of the integrated NMOS and PMOS. High power dissipation must be coupled with effective thermal management and prudent CR durations. The integrated PMOS has an rDS(ON) of 0.35. With 2.5A of steady load current on the PMOS device the power dissipation is 2.2W. The thermal impedance of the package is 31 degrees Celsius per watt, resulting in a 68C die temp rise thus limiting the average DC current on the 12V supply to about 2.5A maximum at +85C ambient and imposing an upper limit on the ROCSET resistor. Do not use an RCRSET resistor greater than 15k.
ISL6111
The average current on the -12V supply should not exceed 0.8A. Since the thermal restrictions on the +12V supply are more severe, the +12V supply restricts the use of the ISL6111 to applications where the 12V supplies draw relatively little current. Since both supplies only have one degree of freedom, the value of ROCSET, the flexibility of programming is quite limited. For applications where more power is required on the +12V supply, contact your local Intersil sales representative for information on other Hot Plug solutions. B. Do not try to sense voltages across the external sense resistors that are less than 20mV as spurious faults due to noise and comparator input sensitivity may result. The minimum recommended RCRSET value is 3.0k. This will set the nominal OC voltage thresholds at 39mV and 26mV for the 3.3V and 5V comparators respectively. C. Minimize VRSENSE so as to not significantly reduce the voltage delivered to the adapter card. Remember PCB trace and connector distribution voltage losses also need to be considered. Make sure that the RSENSE resistor can adequately handle the dissipated power. For best results use a 1% precision resistor with a low temperature coefficient. D. Minimize external FET rDS(ON). Low rDS(ON) or multiple MOSFETs in parallel are recommended.
TABLE 1. SUPPLY +3.3V ICR +5.0V ICR +12V ICR -12V ICR NOMINAL CURRENT REGULATION LEVEL (10%) FOR EACH SUPPLY ((100A x RCRSET)/8.54)/RRSENSE ((100A x RCRSET)/12)/RRSENSE (100A x RCRSET)/0.7 (100A x RCRSET)/3.3
Delaying the time to latch-off works against this primary concern so understand the limitations and realities. Since we use the same CRTIM cap timing cap for all supplies, we have to set that cap to a size large enough to allow the -12V to start up under the worst load for a given system. If we set this to a 75ms duration, then this 75ms time-out duration will also be used when one of the higher power supplies goes into current limiting after startup is complete. The highest power supplies, the 3.3V and 5V each run to a maximum of 25W, as allowed by the PCI spec. If our overcurrent duration is set to 75ms, then theoretically (but extremely unlikely) more than 25W can be dissipated in the external FET for that whole duration. The ISL6111 has a way over-current "WOC" circuit that faults the chip off instantly if this theoretical dead short happens so quickly that the current limiting circuitry can't keep up. In reality, overcurrent is more likely to not be a zero-ohm short, and only a fraction of the power is dissipated in the FET. Ensure adequate sizing of external FETs to carry additional current during CR period in linear operation. By looking at the SOA of the Siliconix Si4404DY FET and even presupposing the full 25W for 100ms duration for a single pulse is not an issue with this power FET. This FET is representative of FETs for a PCI application. If for a higher power non PCI design, consult the MOSFET vendor SOA curves.
Application Considerations
Soft Start and Turn-Off Considerations
The ISL6111 does allow the user to select the rate of ramp up on the voltage supplies. This start-up ramp minimizes inrush current at start-up while the on card bulk capacitors charge. The ramp is created by placing capacitors on M12VG, 3VG and 5VG to ground. These capacitors are each charged up by a nominal 25A current during turn on. The +12VO has internal current controlled ramping circuitry. The same value for all gate timing capacitors is recommended. The gate capacitors must be discharged when a fault is detected to turn off the power FETs thus, larger caps slow the response time. If the gate capacitors are too large the ISL6111 may not be able to adequately protect the bus or the power FETs. The ISL6111 has internal discharge FETs to discharge the load when disabled. Upon turn-off these internal switches on each output discharge the load capacitance pulling the output to gnd. These switches are also on when ENABLE is low thus an open slot is held at the gnd level.
Current Regulation Delay Time to Latch-Off
The CR time delay to latch-off, allows for a predetermined delay from the start of CR, to the simultaneous latch-off of all four supply switches to the load. This delay period is set by the capacitor value to ground from the CRTIM pin. This feature allows the ISL6111 to provide a current regulated soft start into all loads, and to delay immediate latch-off of the bus supply switches thus ignoring transient OC conditions. See Table 2. for CR duration vs CRTIM capacitance value.
TABLE 2. CRTIM, VALUE Nominal CR Duration 0.022F 3.3ms 0.1F 15ms 1F 150ms
Recommended PCB Layout Design
To ensure accurate current sensing and control, the PCB traces that connect each of the current sense resistors to the ISL6111 must not carry any load current. This can be accomplished by two dedicated PCB kelvin traces directly from the sense resistors to the ISL6111, see examples of correct and incorrect layouts below in Figure 2. To reduce
Nominal CR Duration = 150k X TIM cap value.
Caution: An additional concern about long CR durations along with MB supply droop is power-FET survivability. The primary purpose of a protection device such as the ISL6111 is to quickly isolate a faulted card from the voltage bus. 9
ISL6111
parasitic inductance and resistance effects, maximize the width of the high-current PCB traces. ISL6111 is simply grounded. The Fault-not output, FLTN pulls low once the CR duration has expired and signals that all supplies have been disconnected from the load. See Figure 3 for operational PGOOD and FLTN waveforms.
CORRECT
INCORRECT PGOOD / FLTN 5/DIV
TO ISL6111 VS AND VISEN
TO ISL6111 VS AND VISEN 5IOUT 5A/DIV CR = 7.2A CURRENT SENSE RESISTOR 5VOUT 2/DIV
FIGURE 2. SENSE RESISTOR PCB LAYOUT
CRTIM 2V/DIV 20ms/DIV
PGOOD vs Power is Good and Fault Signals
Keep in mind that the -12VOUT is not monitored for under voltage, thus the PGOOD output signal only takes into account the three positive supplies. PGOOD will assert once all minimum positive UV criteria is reached and the M12VO may not be more than a few volts below ground at that time. It will pull low once any positive voltage < UV Vth. For applications that don't use -12V, the M12VI pin on the
FIGURE 3. FLTN & PGOOD FUNCTIONAL WAVEFORM
Adjusting the Current Regulation Level
The current regulation level is adjusted by the CRSET resistance to ground value. The ratio of resistance to CR change is not linear but is unidirectional in relationship, see Figures 4-6.
Typical Performance Curves & Waveforms
12 10 8 AMPS AMPS 6 25C 4 0C 2 0 0.1 3 3.5 R_CRSET (k) 4 4.5 0 -12V 3 3.5 4 4.5 85C 0.6 85C 3.3V 0.5 +12V 0.4 0.3 0.2 0C 25C
5V
R_CRSET (k)
FIGURE 4. 3.3V & 5V SLOWLY INCREASING CURRENT TRIP LEVEL vs TEMPERATURE AND RCRSET
FIGURE 5. +12V & -12V SLOWLY INCREASING CURRENT TRIP LEVEL vs TEMPERATURE AND RCRSET
10
ISL6111 Typical Performance Curves & Waveforms (Continued)
13 3.3V, 5V CURRENT TRIP LEVEL (A) 0.55 12V, -12V CURRENT TRIP LEVEL (A) 450 1200
11
PMOS rON +12 (m)
9 3.3V 7 -12V 5 3.0K 5V 3.5K 4.0K
0.3
375 PMOS +12 rON 337 NMOS -12 rON 300 0 25 50 TEMPERATURE (C) 75
1000
0.175
900
0.05 4.5K
800 85
FIGURE 6. NOMINAL CURRENT TRIP LEVEL vs RCRSET
FIGURE 7. rON vs TEMPERATURE
10.75
4.59
2.9
12 UV TRIP (V)
5V UVTRIP (V)
5 UV 4.58 3.3 UV 2.85
10.716
10.70
0
25
50 TEMPERATURE (C)
75
85
4.57
0
25
50 TEMPERATURE (C)
75
85
2.8
FIGURE 8. 12V UV Vth vs TEMPERATURE
FIGURE 9. UV TRIP vs TEMPERATURE
6
10.0 +12V POR_RISING +12V THRESHOLDS (V)
ABS 12V BIAS (mA)
5
9.66
4
9.33 +12V POR_FALLING
3 0 25 50 TEMPERATURE (C) 75 85
9.0
0
25
50 TEMPERATURE (C)
75
85
FIGURE 10. BIAS CURRENT vs TEMPERATURE
FIGURE 11. 12V ENABLE AND RESET THRESHOLD VOLTAGES vs TEMPERATURE
11
3.3V UVTRIP (V)
10.732
NMOS rON -12 (m)
12V
0.425
437
1100
ISL6111 Typical Performance Curves & Waveforms (Continued)
101 CRTIM LATCH OFF THRESHOLD (V) 0 25 50 TEMPERATURE (C) 75 85 2.74
100 IOC SET (A)
2.72
99
2.70
98
97
2.68 0 25 50 TEMPERATURE (C) 75 85
FIGURE 12. CRSET CURRENT vs TEMPERATURE
FIGURE 13. CRTIM THRESHOLD VOLTAGE vs TEMPERATURE
Using the ISL6111EVAL2 Platform
Biasing and General Information
The ISL6111EVAL2 platform (Figure 20) allows a designer to evaluate and modify the performance and functionality of the ISL6111 in a simple environment. The board is made such that the heat dissipating resistors are shielded from users and equipment by being placed on the bottom, despite this the top of the load board still gets hot. Test point names correspond to the ISL6111 device (U1) pins. Along with the ISL6111 on the ISL6111EVAL2 platform are 2 N-Channel power MOSFETs, (Q1- Q2) these are used as the external switches for the +5V and +3.3V supplies to the load. Current sensing is facilitated by the two 5m 1W metal strip resistors (R7, R3), the voltages developed across the sense resistors are compared to references on board the ISL6111. The ISL6111EVAL2 platform is powered through the 5 labeled jacks on the left half of the board, with outputs on the right half. After properly biasing the ISL6111, signal the ENABLE input high (>2.4V), this will turn on the FET switches and apply voltage to the loads resistors and capacitors. Voltage and current measurements can be easily made as the test points facilitate access to IC pins and other critical circuit nodes.
Evaluating Current Regulation Duration
The current regulation (CR) duration is set by the CRTIM capacitor value, C3 to ground. This provides a programmable duration during which the ISL6111 holds the programmed CR level. Once this duration has expired and the ISL6111 is still in CR mode the output voltages will turn off. The intent of any protection device is to quickly isolate the voltage supplies so a faulty load card does not drag down a supply. A duration period too lengthy increases the likelihood of FET switch damage and results in slower isolation of the faulty card from the rest of system. Figures 14 -19 show nominal turn-on, turn-on into OC condition with CR mode waveforms.
12
ISL6111 Typical Performance Curves
EN 10V/DIV
12VOUT 5V/DIV
EN 10V/DIV 12VOUT 5V/DIV +5VOUT 5V/DIV
+5VOUT 5V/DIV
+3.3VOUT 5V/DIV
+3.3VOUT 5V/DIV -12VOUT 5V/DIV
CTIM 1V/DIV
M12VOUT 5V/DIV CTIM 1V/DIV 4ms/DIV 10ms/DIV
FIGURE 14. ISL6111 TURN-ON INTO NOMINAL LOAD
FIGURE 15. ISL6111 TURN-ON INTO M12V OC CONDITION
12IOUT 0.2A/DIV CR = 0.54A
M12IOUT 0.1A/DIV CR = 0.12A
TIM 5V/DIV
12VOUT 5V/DIV
12VOUT 5V/DIV
TIM 5V/DIV
10ms/DIV
10ms/DIV
FIGURE 16. M12VOUT INTO CR (VCRSET = 0.461V)
FIGURE 17. 12VOUT INTO CR (VCRSET = 0.461V)
3.3IOUT 5A/DIV CR = 10.2A
5IOUT 5A/DIV CR = 7.2A
3VG 2V/DIV
3VSUPPLY 1/DIV 5VSUPPLY 2/DIV 3VOUT 1/DIV 5VG 2V/DIV 5VOUT 2/DIV TIM 5V/DIV TIM 5V/DIV 10ms/DIV
10ms/DIV
FIGURE 18. 3.3V INTO CR (VCRSET = 0.461V)
FIGURE 19. 5VOUT INTO CR (VCRSET = 0.461V)
13
ISL6111
FIGURE 20. ISL6111EVAL2 PLATFORM SCHEMATIC AND PHOTOGRAPH
14
ISL6111
TABLE 3. ISL6111EVAL2 BOARD COMPONENT LISTING COMPONENT DESIGNATOR CONTROLLER BOARD U1 Q1, Q2 R3, R7 R5 C3 R1, R4 C1 C6 C2, C5 R2, R6 R9, R10 R11 R8 C4, C8 C9 C7 ISL6111CR PCI HotPlug Controller Siliconix Si4404DY Sense Resistor for 3.3V and 5V Supplies Current Regulation Set Resistor Current Regulation Duration Set Capacitor PGOOD , FLTN Pull-up Resistor 12VI Decoupling Capacitor M12VG Decoupling Capacitor Optional Gate Timing Capacitors 3.3V Load Resistor 5.0V Load Resistor +12V Load Resistor -12V Load Resistor +3.3V and +5.0V Load Capacitors +12V Load Capacitor -12V Load Capacitor Intersil, ISL6111CR PCI HotPlug Controller 4.5m, 30V, 23A Logic Level N-Channel MOSFET or Equivalent WSL-2512 5m, 1% Metal Strip Resistor or Equivalent 4.53k 0805 Chip Resistor 0.47F 0805 Chip Capacitor (CR duration ~70ms) 5k 0402 Chip Resistor 1F 0603 Chip Capacitor 5600pF 0402 Chip Capacitor NOT POPULATED 0805 Chip Capacitor 2.2, 5W 5.1, 5W 47, 5W 240, 2W 2200F 330F 100F COMPONENT NAME COMPONENT DESCRIPTION
15
ISL6111 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L20.5x5
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHC ISSUE C) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.35 2.95 2.95 0.23 MIN 0.80 NOMINAL 0.90 0.20 REF 0.28 5.00 BSC 4.75 BSC 3.10 5.00 BSC 4.75 BSC 3.10 0.65 BSC 0.60 20 5 5 0.60 12 0.75 0.15 3.25 3.25 0.38 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 3 10/02 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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